1. Field of the Invention
The present invention relates to an AC sensing method memory circuit, and more particularly to a memory circuit capable of suitably detecting data of memory cells even though the data capacity is increased.
2. Description of the Related Art
There has been an increasing demand to increase the capacity of nonvolatile semiconductor memory, which is one kind of semiconductor memory circuit, and to reduce the voltages thereof. The voltage reduction is directed toward the conservation of electric power by enabling operation at lower voltages. This voltage reduction is accompanied by a trend toward a reduction in the cell current that is able to flow in the memory cells. On the other hand, an increased capacity involves longer word lines and bit lines in the cell array and an increase in the number of cells which are connected to these lines, which results in a larger capacitance. In addition, the word lines and bit lines, and the like, become finer and the resistance thereof increases accordingly. Such an increase in the RC (Resistance and Capacitance) value results in an increase in the delay when the word lines are driven by a word driver and when select lines are driven, together with an increase in the delay in the discharge of a bit line potential by a cell current.
More particularly as a result of the increase in the bit-line RC value, the DC sensing method, which detects cell data by converting the change in a bit line current, in accordance with the presence or absence of a cell current while a current is flowing in the bit line, into a voltage, is becoming an obsolete sensing method.
An AC sensing method has been proposed in place of this DC sensing method. According to this AC sensing method, the bit lines are pre-charged to a certain potential, and after the bit lines have assumed a floating state, the bit lines are discharged by a cell current for a predetermined period, and cell data is detected on the basis of whether the bit line potential is discharged to a predetermined potential. Because current is not supplied to the bit lines during sensing, the readout sensitivity can be kept high even if the cell current is small.
FIG. 1 is a circuit diagram of a NAND-type flash memory which is one kind of conventional nonvolatile memory. A memory cell array MCA is provided with a plurality of local bit lines LBL0-0 to LBL1-1, and word lines WL0-0 to WLn-1, and memory cell transistors MC that comprise a floating gate or trapping gate are disposed in the positions of intersection between the bit lines and word lines. In the example in FIG. 1, a pair of local bit line pairs are connected via transistors, which are selected by global select signals GSG1 and GSG2, to global bit lines GBL0 and GBL1. Further, there are n+1 memory cells MC which each constitute a single cell string CSTG, and the cell strings CSTG are connected to local bit lines LBL via transistors selected by select signals SG1-0 and SG1-1 and are connected to a ground potential ARVSS in the memory cell array via transistors which are selected by select signals SG2-0 and SG2-1. Further, each local bit line LBL is connected to a power supply circuit 101, and assumes a different potential or state during programming and erasure operations, and at other times.
The global bit lines GBL0 and GBL1 are connected to respective page buffers 100, and the page buffers are connected to the cell strings of selected memory cells via the global bit lines GBL and local bit lines LBL. The page buffers 100 buffer write data which is supplied from outside during programming and output this data to the memory cells. Also, during read and verify operations and so forth, the page buffers 100 detect a bit line potential which changes in accordance with the presence or absence of a cell current in the memory cells, whereby the cell data is read out.
FIG. 2 is a circuit diagram of a page buffer that comprises a latch circuit 10, which is connected to an input/output terminal I/O (not shown), and transistors P1 and N1 to N5. Further, FIG. 3 is a circuit diagram of a power supply circuit. The power supply circuit 101 comprises a NOR gate 12 and transistors P6, P7 and N8, and generates a bit line bias potential BLBIAS. In other words, during programming, a programming control signal PGM assumes a high level, and an erasure control signal ERS assumes a low level such that the P channel transistors P6 and P7 are both conductive, and the bit line bias potential BLBIAS is then at the level of the supply voltage Vcc. On the other hand, during erasure, the control signals are inverted such that the transistors P6 and N8 are both non-conductive, and the bit line bias potential BLBIAS then assumes a floating state, being otherwise at ground potential.
A description follows for a conventional AC sensing method by means of a page buffer circuit. FIG. 4 is a timing chart of a conventional AC sensing operation during reading. A read operation comprises a preset period T0 which resets the latch circuit 10 in the page buffer, a pre-charge period T1 for pre-charging the bit lines, and a sense period T2 which detects data from a change in the bit line potential as a result of the bit lines being discharged in accordance with the presence or absence of a cell current.
In the preset period T0, the control signals are: BIAS=Vcc (high level), BLCNTL=Vcc, PGMON=Vcc, DIS=Vcc, GSG1=Vcc+α, GSG2=0v, SG1-0=0v, SG2-0=0v, and the selected word line WL0-0=0v, the unselected word line WLS-0=Vcc+α, and BLBIAS=0v. Accordingly, the discharge transistor N2 is conductive as a result of the signal DIS, and the nodes A and B of the latch circuit 10 in the page buffer 100 are preset to a low level and a high level respectively. Further, the global bit lines GBL0 and GBL1, and the local bit lines LBL0-0, LBL1-0, LBL0-1, and LBL1-1 are 0v. Further, for an unselected cell string, SG1-1=0v, SG2-1=0v, WL0-1=WLn-1=floating state.
Thereafter, in the pre-charge period T1, the control signals are such that BIAS=Vss (low level), the transistor P1 is conductive, the signal BLCNTL is a voltage high enough to permit the global bit lines and the local bit lines to be at the pre-charge level, GSG1=VCC+α, GSG2=0v, SG1-0=VCC+α, SG2-0=0v, the selected word line WL0-0=0v, and the unselected word line WLS-0=VCC+α. By applying the supply voltage Vcc to the bit lines via the respective pre-charge transistor P1 in the page buffers which is caused to conduct by the signal BIAS, the global bit lines GBL0 and GBL1 and the local bit lines LBL0-0 and LBL0-1 are pre-charged. Accordingly, the respective sense node SNS in the page buffers is also at a high level. Further, the unselected local bit lines remain LBL1-0=0v, and LBL1-1=0v as a result of the bias potential BLBIAS of the power supply circuit 101.
Further, in the sense period T2, the control signal BIAS is restored to a high level and the pre-charge transistor P1 is non-conductive, thus breaking the current supply circuit for supplying current to the bit lines. Further, when the control signal BLCNTL is at a predetermined level, the select signal SG2-0=Vcc+α, and the cell string CSTG is connected to the array ground voltage ARVSS. As a result, when a memory cell MC is in an erased state (data 1) and the threshold thereof is lower than ground, the bit line is discharged on account of the generation of a cell current (see the solid line in the FIG. 4). Further, when a memory cell MC is in a programmed state (data 0) and the threshold thereof is high, no cell current is generated and hence the bit line is not discharged (see the broken line in the FIG. 4). A change in the potential of the bit line brings about a change in the sense node SNS in the page buffer, and in response to a set signal SET that is generated with predetermined timing, the level of the sense node SNS is latched by the nodes A and B of the latch circuit 10.
FIG. 5 is a timing chart of a conventional program verify operation. In a program verify operation, after a programming pulse is applied to memory cells, it is detected whether or not the threshold voltage thereof is equal to or more than the program verify level by setting the word lines to the program verify level to read out the cell data. Therefore, this operation is basically the same as the read operation of FIG. 4. This operation is different in that the latch circuit 10 in the page buffer is not preset during the preset period T0 and in that the level of the selected word line is not 0V but instead a positive value that is sufficient to secure a programming margin. Therefore, in FIG. 5, in the pre-charge period T1 and the sense period T2, the selected word line WL0-0 is controlled to be 1V.
As described above, the cell current decreases in accordance with a voltage reduction, and the capacitance and resistance of the bit lines increase in accordance with an increased capacity. Accordingly, the voltage discharge period, which pertains to the position at which the bit line is connected to the page buffer, when a bit line is discharged by a cell current and the sense node SNS in the page buffer accordingly changes to a low level, differs depending on the position of the selected memory cell. That is, when a memory cell that is disposed close to the page buffer 100 is selected, the discharge of the bit line propagates to the page buffer rapidly, and when a memory cell that is disposed a long way from a page buffer is selected, the discharge of the bit line propagates to the page buffer slowly.
In addition, in a memory cell that is disposed close to the word driver for driving the word lines, the rise in the word line and in the select line of the cell string is rapid, meaning that the initiation of the discharge is also rapid, whereas in a memory cell that is disposed a long way from the word driver, the rise in the word line and the select line is slow and the initiation of the bit line discharge is accordingly also slow. Examples in which the rise in the unselected word line WLs-0 and in the select line SG2-0 is slow are indicated by the broken lines in FIGS. 4 and 5. In this case, the timing for the initiation of the pre-charging of the bit lines is slow and therefore if the timing of the sense timing signal SET is fixed, only an inadequate discharge time interval is obtained.
On the other hand, in a conventional AC sensing method, because the pre-charge operation and the sensing operation are performed by means of the same timing irrespective of the positions of selected memory cells, when there are variations in the timing with which the discharge of the bit lines in the sensing operation is transmitted to the page buffers, the level of the detected sense node differs. This means that the threshold voltage distribution of the memory cell is extraordinarily wide and the memory reliability is therefore low.
The above problem similarly exists during a read operation and a program verify operation, and is also the same during an erase verify operation.